Conventional SRAM cells consist of planar MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors) on silicon substrates such as bulk wafer or SOI (Silicon On Insulator) wafer.
However, it will be difficult for a bulk planar MOSFET to suppress increase of a short channel effect. This means that a leak current will increase.
In order to avoid this problem, Patent Document 2 mentioned below discloses a SRAM device using four-terminal double-gate FETs (Field-Effect Transistors) that is disclosed in Patent Document 1 mentioned below.
FIG. 1 shows a schematic diagram of the four-terminal double-gate FET disclosed in Patent Document 1. The four-terminal double-gate FET comprises an SOI substrate having a layered structure of a semiconductor substrate 108 and an insulating film 107, a standing semiconductor thin plate 100 on the SOI substrate, a first gate that is on one side of the semiconductor thin plate 100 and consists of a first gate electrode 103 and a first gate insulating film 104, a second gate that is on the other side of the semiconductor thin plate 100 and consists of a second gate electrode 105 and a second gate insulating film 106, a source electrode 101 and a drain electrode 102, both of which are in contact with the standing semiconductor thin plate 100. Unlike FIG. 1, the source and drain electrodes can partly overlap with the first gate electrode 103 and the second electrode 105.
FIG. 2 shows symbols in a circuit diagram of the FET. The first gate electrode 103, the second gate electrode 105, the source electrode 101 and the drain electrode 102 correspond to 203, 204, 201 and 202, respectively, in an n-channel four-terminal double-gate FET 200, and correspond to 208, 209, 206 and 207, respectively, in a p-channel four-terminal double-gate FET 205.
When the four-terminal double-gate FET is used in a logic circuit, a logic signal which is an object of a signal processing is applied to the first gate, while the threshold voltage of the transistor which determines performance such as a processing speed is varied by a bias voltage applied to the second gate. The leakage current of the entire system can be reduced by changing the bias voltage applied to the second gate so as to select a high threshold voltage in a case when a low speed operation is permitted or to select a low threshold voltage in a case when a high speed operation is required.
A configuration example of an SRAM cell using the four-terminal double-gate FETs is disclosed in Patent Document 2. In this document, a flip-flop consists of the four-terminal double-gate FETs, where the first gate and the second gate of the p-channel FET is connected to each other, while the first gate and the second gate of the n-channel FET are used as a logic signal input gate and a threshold voltage control gate, respectively. Thereby, an off-state leakage current of the n-channel FET can be reduced by setting the threshold voltage of the n-channel FET in a standby state high.
Patent Document 3 and 4 mentioned below disclose two different device structures and fabrication methods thereof for further improving the performance of the four-terminal double-gate FET.
Patent Document 3 discloses a method for fabricating the insulating films of the first gate and the second gate such that they have different film thicknesses. By this method, it is feasible to enhance an effect of bias voltage applied to the second gate.
Patent Document 4 discloses a method for fabricating the insulating films of the first gate and the second gate such that they have different permittivities. The effect of bias voltage applied to the second gate can also be enhanced by this method.
Fabrication of such four-terminal double-gate FETs, the method of which are disclosed in each of the above patent document and therefore not described in detail here, is in general feasible by using a pattern as shown in FIG. 3. Here, 301 is a mask to form a fin, 302 is a mask to form gates, 303 and 304 are patterns to form contacts implemented in the mask of the same layer, that is 303 is a contact layer for the interconnection line for the fin, and 304 is a contact layer for the interconnection line for the gates. The gates which is crossing the standing semiconductor thin plate structure and depicted as a single FIGURE are deposited as shown in FIG. 3, and then may be separated so that the deposited gate structure formed on both sides of the standing semiconductor thin plate can act as the first gate and the second gate operating independently from each other.
However, the conventional SRAM has the following problems. In the SRAM circuit shown in Patent Document 2, leakage current can be reduced when the n-channel FET in the flip-flop is off. However, due to the property of the flip-flop circuit, when an n-channel FET in an inverter is off, an n-channel FET in the other inverter is on, so that the off current in this side cannot be reduced effectively. Therefore, a method for reducing the off current of a p-channel FET similarly to the n-channel FET is required.
In addition, although a circuit configuration to reduce a leakage current in the n-channel FETs is off is disclosed in Patent Document 2, a device structure, an arrangement method thereof and an interconnection method for integrating the FETs are not disclosed, and any appropriate method is not known. That is, although some effective layout methods are known for the conventional and standard device such as a planar MOSFET (Metal-Oxide-Semiconductor Field-Effect-Transistor) as described in, for example, Non-Patent Document 1, these methods can not be applied efficiently to the four-terminal double-gate FETs. Accordingly, it is required to realize a large scale integrated SRAM device by fabricating an SRAM cell using the four-terminal double-gate FETs in a small area.
The reason why the layout technique for the conventional MOSFETs can not be applied efficiently is that the four-terminal double-gate FET has two gates unlike the planar MOSFET, so that the number of contacts between the interconnection layers and the gates increases, which increases the area of the device. A new device layout which enables the interconnection lines to share gate contacts on the same node of the circuit topology as much as possible is required.
At the same time, as many contacts as possible connected to the same interconnection line are require to be aligned on a straight line in the new layout in order to reduce the complexity of the interconnection line and suppresses an increase in the area.    Patent Document 1: Japanese Unexamined Patent Application No. 2002-270850    Patent Document 2: Japanese Unexamined Patent Application No. 2005-260607    Patent Document 3: Japanese Unexamined Patent Application No. 2005-167163    Patent Document 4: Japanese Unexamined Patent Application No. 2005-174960    Non-Patent Document 1: J. Davis et al. “A 5.6 GHz 64 kB Dual-Read Data Cache for the POWER6 Processor”, Visual Supplement 2006 to the Digest of Technical Papers of IEEE International Solid-State Circuits Conference, p. 514